Verilog (Aiman)
  *Register file (can register files be made simiper? need to dispay specfic registers [actual bits])
  *Why not model sim (still requeres software which version will change and large knowledge overhead) Not used in testing bc Stoychev says it relies too much on it.  Wouldn't work bc of boot sequence
  *Each component is a verilog version of current project -> Circut diagram and verilog code 
  *Wires teleport
  *closer to class the better
Webassembly C (Colby)
  *Undergrad doesnt have to understand this project
  *Port Java to JS
JS Assembler (Eric)
  *In termail it outputs machine code, which is used in cpu
  *What is high and low in file?  Historical reasons for this designs
  *Wanted bubblesort in 16 bytes of code (need 24)
  *Seperate module to load code, overrides existing register file
  *Doubled again with BIOS
  *User data is needed so it can clear registers
  *Want both optins(dialog box for assembly or upload file)
  *Parsing to remove comments, format, then run it through
  *File level interface and creates 3 files
(Bryce)
  *Does it need to reproce any errors in hardware? Could exist but unlikely.  We arent simulating hardward just the workflow of design. 
  *Boot sequence - Do we need to simulate?  It is the same thing.  Could add BIOS (read only memory) From interface pov, that might be a differnt code to load user code instead
  *BIOS seqment can write to anywhere in code sequment (Kernal touching any part of memory)
  *First code line must be null (no op instruction) impossible to reset to not 0x0 (Aiman looks into)
Server and Webpage(Brady)
  *Set up a webpage on local home server (tested and works)
  *Trying to figure out how to run js
  *No domain name yet (fine for now)
  *No scrolling
  *Check out Senior design webpage 
(Jacob)
  *How do you want seven seg?  Refer to videos 
  
 Other
   *Wanted to load file not accomplish yet
   *Seperate meeting maybe about JS assembler
   *If two labels are the same, program errors
   *Post on meeting details