Visual Debugger for the i281 CPU
i281 Processor, Visualised.
The i281 CPU was made by Dr. Stoytchev and his TA, Kyung-Tae Kim (Jay). The intention was to build a simple processor capable of demonstrating the collective knowledge learned throughout the semester in CprE281. This processor was to be simulated on ther Altera DE2-115 FPGA. Dr. Stoytchev has called the process of development of the i281 as "... a rediscovery of the MIPS processor". However, the incorporation of the processor into the Digital Logic class came not without issues. Namely;
- Visualisation
- Assembling/Dissasembling
- Debugging/Adding New Functions
Visualisation was being done via PowerPoint animations with many slides. Of course this is not ideal as Dr. Stoytchev would rather provide a more hands on approach to his students. PowerPoint animations would only cover set cases of operations with set programs. With a visualiser, a student would be able to feed instructions to a visualiser and watch individual bits being propagated though the processor. Hopefully, this will aid with understanding how each bit activates a module to process instructions and produce and output.
The Assembler will be web-based, and it will allow a student to Assemble assembly code into machine code. Assembly is a relatively new concept to students in 281, so converting to machine code can be quite tricky. The application will use color-coded values to teach the students how the assembly is converted into machine code. It will also have a list of example programs that the students can use.
Students in CprE281 will be introduced to Digital Logic design within the Altera Quartus program. With this in mind, Dr. Stoytchev and Jay opted to create the entire i281 processor in Block Diagram Files. However, this made it very tedious to debug the processor. Block Diagram Files are not able to be debugged via ModelSim. Brute-force hardware testing by flipping switches was done to debug the CPU. The consequence of this becomes the inability to streamline the debugging process via testbenches. In addition to that, unresolved bugs are likely to hinder further development of the CPU. By converting the processor to a hardware design language (HDL), in this case, Verilog, these issues can be solved. Debugging will be much more streamlined as ModelSim does support Verilog. The bonus is that students viewing the Verilog version of the processor will be exposed to HDLs will be able to learn more about using specific primitive modules hidden deep in Quartus' documentation.
With that in mind, Team sdmay21-38 will work to overcome those issues and present solutions to Dr Stoytchev at the end of Spring 2021 for use in the following semester. We, as a team, are confident in our ability that has been garnered by our time at Iowa State University.
